Logic Synthesis and Verification Algorithms 1996th Edition by Gary D. Hachtel (PDF)

Description

This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.

User’s Reviews

Editorial Reviews: From the Back Cover In the last decade logic synthesis has gained widepsread acceptance by designers. Formal verification is now advancing along the same path. Computer aided design tools for logic synthesis and verification have become the primary instrument for coping with the ever increasing complexity of designs, and ever more stringent time-to-market constraints. Effective design must be based on thorough understanding of the capabilities, limitations, and algorithmic principles employed by these tools. In this book we provide a foundation for such understanding.Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization.Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text. The rich collection of examples and solved problems make this book ideal for self study.Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering.

Reviews from Amazon users which were colected at the time this book was published on the website:

⭐I had the oppurtunity to study this book in my graduate study. I think it is a well-written book, which has a substantial coverage of the field of logic synthesis and verification. I would highly recommend this book to advanced readers and those who are mathematically inclined. The expertise of the authors is reflected in the content of the book, and this can be fully appreciated by the readers having the qualifications mentioned above.

⭐This is a very readable book that includes many helpful examples and exercises.Hachtel’s exposition is rigorous and

⭐crystal clear.

⭐As an electrical engineer, reading this book is hell. The author–keeps–using em dashes constantly and it is very annoying. This book is made for mathematicians, complex notation out of nowhere and without explanations of what the notation is. So much of the content is not that difficult but explained in a way with such complex notation for no reason. Is it so hard to write in plain English?

⭐

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